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256Mb SDRAM
Ordering Information
EM 48 8M 32 4 4 V B A - 8 F
EOREX Logo F: PB free package Power Blank : Standard L : Low power I : Industrial
EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM
: : : : : :
40 41 42 43 46 48
Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank
Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 5ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz )
Revision A : 1st B : 2nd C : 3rd D :4th G: for VGA version only
Interface V: 3.3V R: 2.5V
Package C: CSP B: FBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP
URL: http://www.eorex.com Email: sales@eorex.com
Rev.01
1/33
256Mb SDRAM
256Mb( 4Banks ) Synchronous DRAM
EM488M3244VBA (8Mx32)
Description
The EM488M3244VBA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 2Meg words x 4 banks x 32 bits. All inputs and outputs are synchronized with the positive edge of the clock . The 256Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system. It also provides auto refresh with power saving / down mode. All inputs and outputs voltage levels are compatible with LVTTL.
Features
* Fully synchronous to positive clock edge * Clock frequency :125MHz(max) * Single 3.3V +/- 0.3V power supply * LVTTL compatible with multiplexed address * Programmable Burst Length ( B/ L ) - 1,2,4,8 or full page * Programmable CAS Latency ( C/ L ) - 2 or 3 * Data Mask ( DQM ) for Read/Write masking * Programmable wrap sequential - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ) * Burst read with single-bit write operation * All inputs are sampled at the positive rising edge of the system clock. * Auto refresh and self refresh * 4,096 refresh cycles / 64ms (15.6us/row) * FBGA package is lead free solder (Sn-Ag-Cu)
* EOREX reserves the right to change products or specification without notice.
Rev.01
2/33
256Mb SDRAM
Pin Assignment ( Top View )
90-ball FBGA
1 2 3 4 5 6 7 8 9
A B C D E F G H J K L M N P R
OOO
DQ26 DQ24 VSS
O
VDD
O
DQ23
O
DQ21
OOO
DQ28 VDDQ VSSQ
O
VDDQ
O
VSSQ
O
DQ19
OOO
VSSQ DQ27 DQ25
O
DQ22
O
DQ20
O
VDDQ
OOO
VSSQ DQ29 DQ30
O
DQ17
O
DQ18
O
VDDQ
OOO
VDDQ DQ31 NC
O
NC
O
DQ16
O
VSSQ
OOO
VSS DQM3 A3
O
A2
O
DQM2
O
VDD
OOO
A4 A5 A6
O
A10
O
A0
O
A1
OOO
A7 A8 NC
O
NC
O
BA1
O
A11
OOO
CLK CKE A9
O
BA0
O
/CS
O
/RAS
OOO
DQM1 NC NC
O
/CAS
O
/WE
O
DQM0
OOO
VDDQ DQ8 VSS
O
VDD
O
DQ7
O
VSSQ
OOO
VSSQ DQ10 DQ9
O
DQ6
O
DQ5
O
VDDQ
OOO
VSSQ DQ12 DQ14
O
DQ1
O
DQ3
O
VDDQ
OOO
DQ11 VDDQ VSSQ
O
VDDQ
O
VSSQ
O
DQ4
OOO
DQ13 DQ15 VSS
O
VDD
O
DQ0
O
DQ2
(Top view)
Rev.01
3/33
256Mb SDRAM
Pin Descriptions ( Simplified )
Pin
CLK /CS CKE
Name
System Clock Chip select Clock Enable
Pin Function
Master Clock Input(Active on the Positive rising edge) Selects chip when active Activates the CLK when "H" and deactivates when "L". CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row address (A0 to A11) is determined by A0 to A11 level at the bank active command cycle CLK rising edge. CA(CA0 to CA8) is determined by A0 to A8 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10 = High at the pre-charge command cycle, all banks are pre-charged. But when A10 = Low at the pre-charge command cycle, only the bank that is selected by BA is pre-charged. Selects which bank is to be active.
A0 ~ A11
Address
BA0~BA1
Bank Address
/RAS
Row address strobe
Latches Row Addresses on the positive rising edge of the CLK with /RAS "L". Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access.
/CAS
Column address strobe
/WE
Write Enable
DQM0 ~ DQM3
Data input/output Mask
DQM controls I/O buffers.
DQ0 ~ 31
Data input/output
DQ pins have the same function as I/O pins on a conventional DRAM.
VDD/VSS VDDQ/VSSQ NC
Power supply/Ground Power supply/Ground No connection
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. This pin is recommended to be left No Connection on the device.
Rev.01
4/33
256Mb SDRAM
Block Diagram
A0 A1 A2 A3
Row Add. Buffer
Auto/Self Refresh Counter
DQM
Row Decoder
A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1
Address Register
Memory Array
Write DQM Control
Data In S/A & I/O gating Col. Decoder Data Out DQi
Col. Add. Buffer
Read DQM Control
Mode Register Set
Col. Add. Counter DQM /WE DQM Burst Counter
Timing Register
CLK /CLK
CKE
/CS
/RAS
/CAS
Rev.01
5/33
256Mb SDRAM
Commands
Mode register set command ( /CS, /RAS, / CAS, /WE = Low )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
The EM488M3244VBA have a mode register that defines how the device operates. In this command, A0 through BA are the data input pins. After power on, the mode register set command must be executed to initialize the device. The mode register can be set only when all banks are in idle state. The EM488M3244VBA, cannot accept any other commands,only during 2CLK can following this command.
( Figure. 1 Mode register set command )
Active command ( /CS, /RAS = Low , /CAS, /WE = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H' Row Row
The EM488M3244VBA have 4 banks, each with 4,096 rows. This command activates the bank selected by BA and a row address selected by A0 through A11.This command corresponds to a conventional DRAM's /RAS falling.
( Figure. 2 Row address strobe and bank activate command )
Rev.01
6/33
256Mb SDRAM
Precharge command ( /CS, /RAS, /WE = Low , / CAS = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
This command begins precharge operation of the bank selected by. When A10 is high,all banks are precharged, regardless of. When A10 is low,only the bank selected by BA is precharged.
( Figure. 3 Precharged command )
Write command ( /CS, /CAS, /WE = Low, /RAS = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
Column
If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clicks.
( Figure. 4 Column address and write command )
Rev.01
7/33
256Mb SDRAM
Read command ( /CS, /CAS = Low , / RAS, /WE = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
Column
Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column.
( Figure. 5 Column address and read command )
Auto refresh command ( /CS, /RAS, /CAS = Low, /WE, CKE = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
This command is a request to begin the CBR refresh operation. The refresh address is generated internally. Before Executing CBR refresh, all banks must be precharged. After this cycle, all banks will be in the idle (Precharged ) state and ready for a row activate command. During tRC period ( from refresh command to refresh or activate command ), the EM488M3244VBA cannot accept any other command.
( Figure. 6 Auto refresh command )
Rev.01
8/33
256Mb SDRAM
Self refresh entry command ( /CS, / RAS , /CAS, CKE = Low , /WE = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the memory exits the self refresh mode. During self refresh mode, refresh interval and refresh operation are performed internally, so there before is no need for external control. Before executing self refresh, both banks must be precharged.
( Figure. 7 Self refresh entry command )
Burst stop command ( /CS, /WE = Low, /RAS, /CAS = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H'
This command can stop the current burst operation.
( Figure. 8 Burst stop command in full page mode )
Rev.01
9/33
256Mb SDRAM
No operation ( /CS = Low, / RAS , /CAS, /WE = High )
CLK /CS /RAS /CAS /WE BA A10 CKE Add
`H`
This command is not execution command so there is no operations begin or terminate by this command.
( Figure. 9 No operation )
Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following: 1. CLK,CKE,/CS,DQM,DQ pin keep low till power stabilizes, and the CLK pin is stabilized whin 100us after power stabilizes before the following initialization sequence. 2. To stabilize internal circuits, when power is applied, a 200us or longer pause must precede any signal toggling. 3. After the pause, all banks must be precharged using the precharged command ( The precharge all banks command is convenient ). 4. Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. 5. Two or more Arto refresh must be performed.
Remanks: 1. The sequence of Mode register programming and Refresh above may be transposed. 2. CKE and DQM must be held high until the precharge command is issued to ensure data-bus Hi-Z.
Rev.01
10/33
256Mb SDRAM
Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits BA through A0 as data inputs. The register retains data until it is reprogrammed or the device loses power.
Options
BA through A7
/CAS Latency
A6 through A4
Wrap type
A3
Burst Length
A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK elapsed.
/CAS Latency
/CAS Latency is the most critical of the parameters begin set. It tells the device how many clocks must elapse before the data will be available.
Burst Length
Burst length is the number of the words that will be output or input in a write cycle. After a read burst is completed, the output bus will become Hi-Z. The burst length is programmable as 1,2,4,8 or full page.
Wrap Type ( Burst Sequence )
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either Sequence or Interleave. The method chosen will depend on the type of CPU in the system. Some microprocessor cache systems are optimized for sequential addressing and others for interleaved.
Rev.01
11/33
256Mb SDRAM
Simplified State Diagram
Self Refresh
LF SE LF SE
it Ex
Mode Register Set
MRS
IDLE
REF
CBR Refresh
CK E CK E
Write
Row Active
ad Re w it
w it h
ACT
Power Down
CKE
BS Re T ad
CKE
Read
Active Power Down
WRITE Suspend
CKE CKE
Wr ite
h
WRITE
Read
READ
Write
CKE
READ Suspend
CKE
PR E
WRITEA Suspend
CKE
WRITEA
E PR
READA
CKE
CKE
CKE
READA Suspend
POWER ON
Precharge
Precharge
Manual Input Automatic Sequence
Rev.01
12/33
256Mb SDRAM
Address Input for Mode Register Set
BA0/1 A10/11 A9
A8
A7
A6
A5
A4
A3 BT
A2
A1
A0
Operation Mode
CAS Latency
Burst Length
Sequential 1 2 4 8 Reserved Reserved Reserved Full Page
Burst Length Interleave A2 1 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1
A1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1
Burst Type Sequential Interleave
A3 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
BA0/1 A10/11 0 0 0 0
A9 0 1
A8 0 0
A7 0 0
Operation Mode Normal Burst read with Single-bit Write
Rev.01
13/33
256Mb SDRAM
Burst Type ( A3 )
Burst Length 2
4
8
Full Page *
A2 A1 A0 XX0 XX1 X0 0 X0 1 X1 0 X1 1 000 001 010 011 100 101 110 111 nnn
Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Cn Cn+1 Cn+2 ......
Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 -
* Page length is a function of I/O organization and column addressing x32 (CA0 ~ CA8) : Full page = 512 bits
Rev.01
14/33
256Mb SDRAM
Precharge
The precharge command can be issued anytime after tRAS ( min.) is satisfied. Soon After the precharge command is issued, precharge operation performed and the synchronous DRAM enters the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge. The earliest timing in a read cycle that a precharege command can be issued without losing any data in the burst is as follows. It is depends on the /CAS latency and clock cycle time.
0
1
2
3
4
5
6
7
8
CLK
Command ( CL= 2 )
Read
PRE
DQ ( CL= 2 )
Q1
Q2
Q3
Q4
Hi-Z
Command ( CL= 3 )
Read
PRE
DQ ( CL= 3 )
Q1
Q2
Q3
Q4
Hi-Z
BL=4
In order to write all data to the memory cell correctly, the asynchronous parameter tDPL must be satisfied. The tDPL (min.) specification defines the eariliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL(min.) with clock cycle time. In a word, the precharge command can be issued relative to reference clock that indicates the last data word is valid. The minus in the following table means clocks before the reference and the plus means time after the reference.
/CAS latency
2 3
Read
-1 -2
Write
+ tDPL( min.) + tDPL ( min.)
Rev.01
15/33
256Mb SDRAM
Auto precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command ( Read with Auto precharge command or Write with Auto precharge command ), auto precharge is selected and begins automatically. The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. In read cycle, once auto precharge has started , an activate command to the bank can be issued after tRP has been satisfied
Read with Auto Precharge
During a read cycle, the auto precharge begins same as ( /CAS latency of 2 ) or one clock earlier ( /CAS latency of 3 ) the last data word output.
0
1
2
3
4
5
6
7
8
CLK
Command ( CL= 2 )
Read AP
Auto precharge starts
DQ ( CL= 2 )
Q1
Q2
Q3
Q4
Hi-Z
Command ( CL= 3 )
Read AP
Auto precharge starts
DQ ( CL= 3 )
Q1
Q2
Q3
Q4
Hi-Z
BL=4 ( tRAS must be satisfied )
Remanks: Read AP means Read with auto precharge
Rev.01
16/33
256Mb SDRAM
Write with Auto Precharge
During write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL( min.) after the last dataword input to the device.
0
1
2
3
4
5
6
7
8
CLK
Command ( CL= 2 )
Write AP
Auto precharge starts
DQ ( CL= 2 )
D1
D2
D3
D4 tDPL( min. )
Hi-Z
Command ( CL= 3 )
Write AP
Auto precharge starts
DQ ( CL= 3 )
D1
D2
D3
D4 tDPL( min. )
Hi-Z
BL=4 ( tRAS must be satisf ied )
Remanks: Write AP means Write with auto precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the following table minus means clocks before the reference ,plus means after the reference.
/CAS latency
2 3
Read
-1 -2
Write
+ tDPL( min.) + tDPL ( min.)
Rev.01
17/33
256Mb SDRAM
Read / Write command interval
Read to read command interval
During a read cycle, when new Read command is issued,it will be effective after / CAS latency, even if the previous read operation does not completed. Read will be interrupted by another Read. The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.
0
1
2
3
4
5
6
7
8
CLK
Command
Read A
Read B
DQ
1 Cycle
QA1
QB1
QB2
QB3
QB4
Hi-Z
B L = 4, C L = 2
Write to write command interval
During a write cycle, when new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. Write will be interrupted by another Write. The interval between the commands is minimum 1 cycle. Each write command can be issued in every clock without any restriction.
0
1
2
3
4
5
6
7
8
CLK
Command
Write A
Write B
DQ
DA1
DB1
DB2
DB3
DB4
Hi-Z
1 Cycle
B L = 4, C L = 2
Rev.01
18/33
256Mb SDRAM
Write to read command interval
Write and Read command interval is also 1 cycle. Only the write data before read command will be written. The data bus must be Hi-Z at least one cycle prior to the first DOUT.
0
1
2
3
4
5
6
7
8
CLK
Command ( CL = 2 )
Write A
Read B
DQ ( CL = 2 )
DA1
Hi-Z
QB1
QB2
QB3
QB4
Command ( CL = 3 )
Write A
Read B
DQ ( CL = 3 )
DA1
Hi-Z
QB1
QB2
QB3
QB4
BL=4
Rev.01
19/33
256Mb SDRAM
Read to write command interval
During a read cycle, Read can be interrupt by Write. The read and write command interval is 1 cycle minimum. There's a restriction to avoid data conflict. The data bus must be Hi-Z using DQM before write.
0
1
2
3
4
5
6
7
8
9
CLK Command DQM
Read
Write
DQ
Hi-Z
D1
D2
D3
D3
BL=4
Read can be interrupted by Write. DQM must be high at least 3 clicks prior to the write command.
0 1 2 3 4 5 6 7 8 9
CLK Command ( CL = 2 )
Read
Write
DQM
DQ ( CL = 2 )
Q1
Q2
Q3 Hi-Z is necessar y
D1
D2
D3
Command ( CL = 3 ) DQM DQ ( CL = 3 )
Read
Write
Q1
Q2 Hi-Z is necessar y
D1
D2
D3
BL=8
Rev.01
20/33
256Mb SDRAM
Burst terminate
There are two ways to terminate a burst operation other than using a Read or a Write command. One is the burst stop command and the other is the precharge command.
Burst stop command
During a read cycle,when the burst stop command is issued, the burst read are terminated and the data bus goes to Hi-Z after the /CAS latency from the burst stop command.
0 1 2 3 4 5 6 7 8 9
CLK Command
Burst Stop
Read
DQ ( CL = 2 )
Q1
Q2
Q3
Hi-Z
DQ ( CL = 3 )
Q1
Q2
Q3
Hi-Z
B L = don't care
During a write cycle,when the burst stop command is issued, the burst write data are terminated and the data bus goes to Hi-Z at the same clock with the burst stop command.
0
1
2
3
4
5
6
7
8
9
CLK Command
Burst Stop
Write
DQ ( CL = 2 /3 )
D1
D2
D3
D4
Hi-Z
B L = don't care
Rev.01
21/33
256Mb SDRAM
Precharge Termination
Precharge Termination in READ Cycle During a read cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same banks can be activated again after tRP from the precharge command. To issue a precharge command , tRAS must be satisfied. When /CAS Latency is 2, the read data will remain valid until two clocks after the precharge command.
0 1 2 3 4 5 6 7 8 9
CLK
Precharge
Command
Read
Activ e
DQ
Q1
Q2
Q3
Q4 tRP
Hi-Z
B L = don't care , CL= 2
When /CAS Latency is 3, the read data will remain valid until two clocks after the precharge command.
0
1
2
3
4
5
6
7
8
9
CLK Command
Precharge
Read
Activ e
DQ
Q1
Q2
Q3 tRP
Q4
Hi-Z
B L = don't care , CL= 3
Rev.01
22/33
256Mb SDRAM
Precharge Termination in Write Cycle During a write cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same banks can be activated again after tRP from the precharge command. To issue a precharge command , tRAS must be satisfied. When /CAS Latency is 2, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. In order to avoid this situation, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
0
1
2
3
4
5
6
7
8
9
CLK
Precharge
Command DQM DQ
Write
Activ e
D1
D2
D3
D4
D5 tRP
Hi-Z
B L = don't care, CL= 2 ( tRAS must be satisfied )
When /CAS Latency is 3, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command. In order to avoid this situation, DQM must be high at the same clock as the precharge command. This will mask the invalid data.
0 1 2 3 4 5 6 7 8 9
CLK
Precharge
Command DQM DQ
Write
Activ e
D1
D2
D3
D4
D5 tRP
Hi-Z
B L =don't care , CL= 3 ( tRAS must be satisf ied )
Rev.01
23/33
256Mb SDRAM
Truth Table
1. Command Truth Table ( EM488M3244VBA )
Command
Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set
Symbol
DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS
CKE
n-1
H H H H H H H H H H H
n
X X X X X X X X X X X
/CS
H L L L L L L L L L L
/RAS /CAS /WE
X H H H H H L L L L L X H H L L L H H H H L X H L H H L H H L L L
BA
X X X V V V V V V X L
A10 A9~A0
X X X L H L H V L H L X X X V V V V V X X V
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
2. DQM Truth Table
Command
Data w rite / output enable Data mask / output disable Upper byte w rite enable / output enable Read Read w ith auto pre-charge Write Write w ith auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set
Symbol
ENB MASK BSTH READ READA WRIT WRITA ACT PRE PALL MRS
CKE
n-1
H H H H H H H H H H H
n
X X X X X X X X X X X
/CS
H L L L L L L L L L L
Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input
3. CKE Truth Table
Command
Activating Any Clock suspend Idle Idle Self refresh Idle Power down
Command
Clock suspend mode entry Clock suspend mode Clock suspend mode exit CBR refresh command Self refresh entry Self refresh exit Pow er dow n entry Pow er dow n exit
Symbol
CKE
n-1
H L L
n
L L H H L H H L H
/CS
X X X L L L H X X
/RAS /CAS /WE Addr.
X X X L L H X X X X X X L L H X X X X X X H H H X X X X X X X X X X X X
REF SELF
H H L L H L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care)
Rev.01
24/33
256Mb SDRAM
4. Operative Command Table
Current state /CS /R
H L L Idle L L L L L H L L Row active L L L L L H L L L Read L L L L L H L L L Write L L L L L X H H H L L L L X H H H L L L L X H H H L L L L L X H H H L L L L L
/C /W
X H L L H H L L X H L L H H L L X H H L L H H L L X H H L L H H L L X X H L H L H L X X H L H L H L X H L H L H L H L X H L H L H L H L
Addr.
X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code
Command
DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Action
Nop or pow er dow n Nop or pow er dow n ILLEGAL ILLEGAL Row activating Nop Ref resh or self refresh Mode register accessing Nop Nop Begin read : Determine AP Begin w rite : Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Continue burst to end Row active Continue burst to end Row active Burst stop Row active Terminate burst, new read : Determine AP Terminate burst, start w rite : Determine AP ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL Continue burst to end Write recovering Continue burst to end Write recovering Burst stop Row active Terminate burst, start read : Determine AP 7, 8 Terminate burst, new w rite : Determine AP 7 ILLEGAL Terminate burst, pre-charging ILLEGAL ILLEGAL
Notes
2 2 3 3
4
5 5 3 6 4
7 7, 8 3 4
7,8 7 3 9
Re m ark H = High level, L = Low level, X = High or Low level (Don't care)
Rev.01
25/33
256Mb SDRAM
Current state
/CS /R
H L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L
/C /W
X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Action
Continue burst to end Precharging Continue burst to end Precharging ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL burst to end Write recovering w ith auto precharge Continue burst to end Write recovering w ith auto precharge ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle af ter tRP Nop Enter idle af ter tRP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle af ter tRP ILLEGAL ILLEGAL Nop Enter idle af ter tRCD Nop Enter idle af ter tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Notes
3 3 3 3
Read w ith AP
L L L L L H L L
Write w ith AP
L L L L L L H L L L
3 3 3 3
3 3 3
Pre charging
L L L L L H L L L
3 3 3,10 3
Row activating
L L L L L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Rev.01
26/33
256Mb SDRAM
Current state
/CS /R
H L L L X H H H H L L L L X H H H H L L L L X H H L L X H H H L
/C /W
X H H L L H H L L X H H L L H H L L X H L H L X H H L X X H L H L H L H L X H L H L H L H L X X X X X X H L X X
Addr.
X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X BA/CA/A10 BA/CA/A10 BA/RA BA, A10 X Op-Code X X X X X X X X X X
Command
DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP/ BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS
Action
Nop Enter row active af ter tDPL Nop Enter row active af ter tDPL Nop Enter row active af ter tDPL Start read, Determine AP New w rite, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter precharge af ter tDPL Nop Enter precharge af ter tDPL Nop Enter precharge af ter tDPL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop Enter idle after tRC Nop Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL
Notes
Write recovering
L L L L L H L L L L L L L L H L
8 3 3
Write recovering w ith AP
3,8 3 3
Refres hing
L L L H L
M ode Regis ter Acces s ing
L L L
Re m ark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Precharge
Notes 1. All entries assume that CKE w as active (High level) during the preceding clock cycle. 2. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Pow er dow n mode. All input buf fers except CKE w ill be disabled. 3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA0/1), depending on the state of that bank. 4. If all banks are idle, and CKE is inactive (Low level), SDRAM w ill enter Self refresh mode. All input buf fers except CKE w ill be disabled. 5. Illegal if tRCD is not satisfied. 6. Illegal if tRAS is not satisfied. 7. Must satisfy burst interrupt condition. 8. Must satisfy bus contention, bus turn around, and/or w rite recovery requirements. 9. Must mask preceding data w hich don't satisfy tDPL. 10. Illegal if tRRD is not satisfied.
Rev.01
27/33
256Mb SDRAM
5. Command Truth Table for CKE
Current state CKE
n-1 n H L Self re fres h L L L L H H H Self re fres h re covery H H H H H H Pow e r dow n L L H H H H Both bank s idle H H H H H H L Row active Any s tate other than lis ted above H L H H L L X H H H H L H H H H L L L L X H L H H H H H L L L L L X X X H L H L
/CS /R
X H L L L X H L L L H L L L X X X H L L L L H L L L L X X X X X X X X X H H L X X H H L X H H L X X X X H L L L X H L L L X X X X X X X
/C /W
X X H L X X X H L X X H L X X X X X X H L L X X H L L X X X X X X X X X X X X X X X X X X X X X X X X X X X H L X X X H L X X X X X X X
Addr.
X X X X X X X X X X X X X X X X X
Action
INVALID, CLK (n - 1) w ould exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) w ould exit pow er dow n Exit pow er dow n Idle Maintain pow er dow n mode Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
Notes
X Op-Code
Refresh Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table Refer to operations in Operative Command Table
X Op-Code X X X X X X
Self refresh Refer t o operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Pow er dow n Refer to operations in Operative Command Table Begin clock suspend next cycle Exit clock suspend next cycle Maintain clock suspend
1 1 1 2
Re m ark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. Self refresh can be entered only from the both banks idle state. Pow er dow n can be entered only from both banks idle or row active state. 2. Must be legal command as defined in Operative Command Table.
Rev.01
28/33
256Mb SDRAM
Absolute Maximum Ratings
Symbol
VIN, VOUT VDD, VDDQ TOP TSTG PD IOS
Item
Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current
Rating
-0.5 ~ 4.6 -0.5 ~ 4.6 0 ~ 70 -55 ~ 125 1 50
Units
V V C C W mA
Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended DC Operation Conditions ( Ta = 0 ~ 70C)
Symbol
VDD VDDQ VIH VIL
Parameter
Power Supply Voltage Power Supply Voltage (for I/O Buffer) Input logic high voltage Input logic low voltage
Min.
3.0 3.0 2.0 -0.3
Typical
3.3 3.3
Max.
3.6 3.6 VDD+0.3 0.8
Units
V V V V
Note : 1. All voltage referred to VSS. 2. VIH (max) = VDD+1.5V for pulse w idth 5ns 3. VIL (min) = VSS-1.5V f or pulse w idth 5ns
Capacitance ( Vcc =3.3V, f = 1M Hz, Ta = 25C )
Symbol
CCLK CI CO
Parameter
Clock capacitance Input capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQM0 ~ 3 Input/Output capacitance
Min.
1.5 1.5 3.0
Max.
3.0 3.0 5.5
Units
pF pF pF
Rev.01
29/33
256Mb SDRAM
Recommended DC Operating Conditions
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70 C, Ta = -40 to 85C )
Parameter
Symbol
Test condition
MAX
Units Notes
Operating current
ICC1
Burst length = 1, tRC =tRC (min), IOL = 0 mA, One bank active CKE VIL (max.), tCk = tck(min) CKE VIL (max.), tCk = CKE VIL (min.), tCK = tck(min), /CS VIH (min.)Input signals are changed one time during 2clk CKE,/CS VIL (min.), tCK = Input signals are stable
125
mA
1
Precharge standby ICC2P current in power down ICC2PS mode ICC2N
3 2 20
mA mA mA
Precharge standby current in non-power down mode
ICC2NS ICC3P ICC3PS
9 4 3
mA mA mA
Active standby current in power down mode
CKE VIL(m ax), tCK = tck(min) CKE VIL(m ax), tCK = CKE VIL(min), tCK = tck(min), / CS VIH(min) Input signals are changed one time during 2clk CKE VIL(min), tCK = Input signals are stable tCCD = 2CLKs , IOL = 0 mA tRC =tRC(min.) VIL 0.2V ,VIH VDD-0.2V
ICC3N Active standby current in non-power down mode ICC3NS operating current (Burst mode) Refresh current Self Refresh current
45
mA
30
mA
ICC4 ICC5 ICC6
150 270 3
mA mA mA
2 3 4
Note : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 2. ICC4 depends on output loading and cycle rates. Specified values are obtained w ith the output open. Input signals are changed only one time during tCK(min) 3. Input signals are changed only one time during tCK(min) 4. Standard pow er version.
Rev.01
30/33
256Mb SDRAM
Recommended DC Operating Conditions ( Continued )
Parameter Symbol Test condition Min. Max. Unit
Input leakage current
IIL
0 VI VDDQ, VDDQ=VDD All other pins not under test=0 V 0 VO VDDQ, DOUT is disabled Io = -2mA Io = +2mA
-1
+1
uA
Output leakage current High level output voltage Low level output voltage
IOL VOH VOL
-1.5 2.4
+1.5
uA V
0.4
V
AC Operating Test Conditions
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70C )
Output Reference Level Output Load Input Signal Level Transition Time of Input Signals Input Reference Level 1.4V / 1.4V CL=30pF 2.4V / 0.4V 2ns 1.4V
Rev.01
31/33
256Mb SDRAM
Operating AC Characteristics
( VDD = 3.3V +/- 0.3 V, Ta = 0 ~ 70C, Ta = -40 to 85C )
Parameter
CL = 3 CL = 2 tCK
Symbol
-8 Min. Max.
8 10 2.5 2.5 2 5.4 -
Units Notes
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK CLK CLK CLK CLK 3 3 3 3 3 2
Clock cycle time
Access time from CLK CLK high level width CLK low level width Data-out hold time
tAC tCH tCL tOH
Data-out high impedance time Data-out low impedance time Input hold time Input setup time ACTIVE to ACTIVE command period ACTIVE to PRECHARGE command period PRECHARGE to ACTIVE command period ACTIVE to READ/WRITE delay time ACTIVE(one) to ACTIVE(another) command READ/WRITE command to READ/WRITE command Data-in to PRECHARGE command Data-in to BURST stop command Data-out to high impedance from CL = 3 PRECHARGE command CL = 2 Refresh time(4,096 cycle)
tHZ tLZ tIH tIS tRC tRAS tRP tRCD tRRD tCCD tDPL tBDL tROH tREF
0 0.8 1.5 67.5
5.4 -
45 120k 20 20 15 1 2 1 3 2 64
ms
Note : 1. All voltages referenced to Vss. 2. tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. 3. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows : The number of clock cycles = Specified value of timing/clock period (Count fractions as a whole number)
Rev.01
32/33
256Mb SDRAM
Package Dimension
* EOREX reserves the right to change products or specification without notice.
Rev.01
33/33

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